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MDT10P21 this spec ification are subject to be changed without notice. any latest information please preview http;//www.mdtic.com.tw p. 1 2004/1 ver. 1.3 1. general description this eprom - based 8 - bit micro - controller uses a fully static cmos design technology to achieve high speed, small size, low power and high noise immunity. on chip memory includes 0.5k words eprom and80 bytes static ram. four comparato r inputs with external vref (not for 18 pin package) are also provided. 2. features u fully cmos static design u 8 - bit data bus u on chip eprom size : 0.5 k words u internal ram size : 80 bytes (72 general purpose registers, 8 special registers) u 36 single word instructions u 14 - bit instructions u 2 - level stacks u operating voltage : 2.3v ~ 5.5 v u operating frequency : 0 ~ 20 mhz u the most fast execution time is 200 ns under 20 mhz in all single cycle instructions except the branch instruction u addressing modes include d irect, indirect and relative addressing modes u built - in power - on reset u 4 channel comparator u power edge - detector reset u sleep mode for power saving u 8 - bit real time clock/counter(rtcc) with 8 - bit programmable prescaler u 4 types of oscillator can be sele cted by programming option: rc ?e low cost rc oscillator lfxt ?e low frequency crystal oscillator xtal ?e standard crystal oscillator hfxt ?e high frequency crystal oscillator u 4 oscillator start - up time can be selected by programming option: 150 m s, 20 ms, 40 ms, 80 ms u on - chip rc oscillator based watchdog timer(wdt) can be operated freely u 12 i/o(for 18 pins package),14 i/o(for 20 pins package),16 i/o(for 22/24 pins package) pins with their own independent direction control 3. applications the application areas of this MDT10P21 range from appliance motor control and high speed automotive to low power remote transmitters/receivers, pointing devices, and telecommunications processors, such as remote controller, small instruments, chargers, toy, automobile and pc peri pheral ? etc
MDT10P21 this spec ification are subject to be changed without notice. any latest information please preview http;//www.mdtic.com.tw p. 2 2004/1 ver. 1.3 4. pin assignment ? a1 ?g 20pins, a2 ?g 22pins, a3 ?g 24pins, a5 :18 pins ? p ?e pdip,s ?e sop, k ?e skinny a1p,a1s pa5 1 20 pa4/vref pa2/cic2 2 19 pa1/cic1 pa3/cic3 3 18 pa0/cic0 rtcc 4 17 osc1 /mclr 5 16 osc2 vss 6 15 vdd pb0 7 14 pb7 pb1 8 13 pb6 pb2 9 12 pb5 pb3 10 11 pb4 a2k pa7 1 22 pa6 pa5 2 21 pa4/vref pa2/cic2 3 20 pa1/cic1 pa3/cic3 4 19 pa0/cic0 rtcc 5 18 osc1 /mclr 6 17 osc2 vss 7 16 vdd pb0 8 15 pb7 pb1 9 14 pb6 pb2 10 13 pb5 pb3 11 1 2 pb4 a3s nc 1 24 nc pa7 2 23 pa6 pa5 3 22 pa4/vref pa2/cic2 4 21 pa1/cic1 pa3/cic3 5 20 pa0/cic0 rtcc 6 19 osc1 /mclr 7 18 osc2 vss 8 17 vdd pb0 9 16 pb7 pb1 10 15 pb6 pb2 11 14 pb5 pb3 1 2 13 pb4 a5p,a5s pa2cic2 1 18 pa1/cic1 pa3/cic3 2 17 pa0/cic0 rtcc 3 16 osc1 /mclr 4 15 osc2 vss 5 14 vdd pb0 6 13 pb7 pb1 7 12 pb6 pb2 8 11 pb5 pb3 9 10 pb4
MDT10P21 this spec ification are subject to be changed without notice. any latest information please preview http;//www.mdtic.com.tw p. 3 2004/1 ver. 1.3 5. block diagram stack two levels program counters oscillator circuit power on reset power down reset 8-bit timer/counter eprom 0.5k ?? 14 (MDT10P21) instruction register instruction decoder working register alu prescale ram 72 ?? 8 special register control circuit status register wdt/ost timer port b port a os c1 os c2 mc lr data 8-bit rtcc 9 bits 9 bits 14 bits port pa 0~p a7 (22,24 pins) pa0~p a5 (20 pins) pa0~p a3 (18 pins) 8 bits port pb0 ~p b7 8 bits d0~d7 comparat or mode register cmr0~c mr5
MDT10P21 this spec ification are subject to be changed without notice. any latest information please preview http;//www.mdtic.com.tw p. 4 2004/1 ver. 1.3 6. pin function description pin name i/o fun ction description pa0~pa7 i/o pa0~pa3 : ttl input level or comparator input pa4 : ttl input level or comparator vref input pa5~pa7 : ttl input level pb0~pb7 i/o port b, ttl input level rtcc i real time clock/counter, schmitt trigger input levels /mcl r i master clear, schmitt trigger input levels osc1 i oscillator input osc2 o oscillator output vdd power supply vss ground nc unused ,do not connect 7. memory map (a) register map address description 00 indirect addressing register 01 rtcc 02 pc 03 status 04 msr 05 port a 06 port b 07 control register for comparator 08~0f internal ram, general purpose register 10~1f internal ram, memory bank 0 30~3f internal ram, memory bank 1 50~5f internal ram, memory bank 2 70~7f internal ram, memory bank 3
MDT10P21 this spec ification are subject to be changed without notice. any latest information please preview http;//www.mdtic.com.tw p. 5 2004/1 ver. 1.3 (1) iar ( indirect address register) : r0 (2) rtcc (real time counter/counter register) : r1 (3) pc (program counter) : r2 write pc, call --- always 0 ljump, jump, lcall --- from instruction word rtiw, ret --- from stack a 8 a7~a0 write pc --- from alu ljump, jump, lcall, call --- from instruction word rtiw, ret --- from stack (4) status (status register) : r3 bit symbol function 0 1 2 3 4 5 - 7 c hc z pf tf ?x?x carry bit half carry bit zero bit power loss flag bit time overflow flag bit general purpose bit (5) msr (memory select register) : r4 memory select register : 00 : 10~1f 01 : 30~3f 10 : 50~5f 11 : 70~7f b7 b6 b5 b4 b3 b2 b1 b0 read only ?1? indirect addressing mode (6) port a : r5 p a7~pa0, i/o register for 22, 24 pins pa5~pa0, i/o register for 20 pins pa3~pa0, i/o register for 18 pins
MDT10P21 this spec ification are subject to be changed without notice. any latest information please preview http;//www.mdtic.com.tw p. 6 2004/1 ver. 1.3 (7) port b : r6 pb7~pb0, i/o register (8) cmr(comparator mode register) : r7 bit function 0 1 2 3 5:4 7:6 0: def ine pa0 as ttl input 1: define pa0 as comparator input 0: define pa1 as ttl input 1: define pa1 as comparator input 0: define pa2 as ttl input 1: define pa2 as comparator input 0: define pa3 as ttl input 1: define pa3 as comparator input reference volta ge select 00: 1/4 vdd 01: 1/2 vdd 10: 3/4 vdd 11: vref (external pin and pa4 must be set to input) register bits (9) tmr (time mode register) bit symbol function prescaler value rtcc rate wdt rate 2 ?x 0 ps2 ?x 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 3 psc prescaler assignment bit : 0 ?x rtcc 1 ?x watchdog timer 4 tce rtcc signal edge : 0 ?x increment on lo w - to - high transition on rtcc pin 1 ?x increment on high - to - low transition on rtcc pin 5 tcs rtcc signal set : 0 ?x internal instruction cycle clock 1 ?x transition on rtcc pin
MDT10P21 this spec ification are subject to be changed without notice. any latest information please preview http;//www.mdtic.com.tw p. 7 2004/1 ver. 1.3 (10) cpio a, cpio b (control port i/o mode register) the cpio register is ?wr ite - only? ? ?0?, i/o pin in output mode; ? ?1?, i/o pin in input mode. (11) eprom option by writer programming : a. first word oscillator type oscillator start - up time rc oscillator 150 m s lfxt oscillator 20 ms xtal oscillator 40 ms hfxt oscillator 80 ms watchdog timer control watchdog timer disable all the time watchdog timer enable all the time power edge detect security bit ped disable security disable ped enable security enable (b) program memory address description 000 - 1ff prog ram memory 1ff the starting address of the power on, external reset or wdt 8. reset condition for all registers register address power - on reset /mclr reset wdt reset cpio a ?e?e 1111 1111 1111 1111 1111 1111 cpio b ?e?e 1111 1111 1111 1111 1111 1111 tmr ?e?e -- 11 1111 -- 11 1111 -- 11 1111 iar 00h ?e ?e ?e rtcc 01h xxxx xxxx uuuu uuuu uuuu uuuu pc 02h 1111 1111 1111 1111 1111 1111
MDT10P21 this spec ification are subject to be changed without notice. any latest information please preview http;//www.mdtic.com.tw p. 8 2004/1 ver. 1.3 register address power - on reset /mclr reset wdt reset status 03h 0001 1xxx 000# #uuu 000# #uuu msr 04h 100x xxxx 100u uuuu 1uuu uuuu port a 05h xxxx xxxx uuuuuuuu uuuu uuuu port b 06h xxxx xxxx uuuu uuuu uuuu uuuu cmr 07h 0000 0000 uuuu uuuu uuuu uuuu note : u ? unchanged, x ? unknown, - ? unimplemen ted, read as ?0? # ? value depends on the condition of the following table condition status: bit 4 status: bit 3 /mclr reset (not during sleep) u u /mclr reset during sleep 1 0 wdt reset (not during sleep) 0 1 wdt reset during sleep 0 0 9. instructio n set instruction code mnemonic operands function operating status 010000 00000000 nop no operation none 010000 00000001 clrwt clear watchdog timer 0 ? wt tf, pf 010000 00000010 sleep sleep mode 0 ? wt, stop osc tf, pf 010000 00000011 tmode load w to tmode register w ? tmode none 010000 00000100 ret return stack ? pc none 010000 00000rrr cpio r control i/o port register w ? cpio r none 010001 1rrrrrrr stwr r st ore w to register w ? r none 011000 trrrrrrr ldr r, t load register r ? t z 111010 iiiiiiii ldwi i load immediate to w i ? w none 010111 trrrrrrr swapr r, t swap halves register [r(0~3) ? r(4~7)] ? t none 011001 trrrrrr r incr r, t increment register r + 1 ? t z 011010 trrrrrrr incrsz r, t increment register, skip if zero r + 1 ? t none 011011 trrrrrrr addwr r, t add w and register w + r ? t c, hc, z 011100 trrrrrrr subwr r, t subtract w from register r ?? w ? t (r+/w+1 ? t) c, hc, z 011101 trrrrrrr decr r, t decrement register r ?? 1 ? t z 011110 trrrrrrr decrsz r, t decrement register, skip if zero r ?? 1 ? t none 010010 trrrrrrr andwr r, t and w and register r ?? w ? t z
MDT10P21 this spec ification are subject to be changed without notice. any latest information please preview http;//www.mdtic.com.tw p. 9 2004/1 ver. 1.3 instruction code mnemonic operands function opera ting status 110100 iiiiiiii andwi i and w and immediate i ?? w ? w z 010011 trrrrrrr iorwr r, t inclu. or w and register r ?? w ? t z 110101 iiiiiiii iorwi i inclu. or w and immediate i ?? w ? w z 010100 trrrrrrr xorwr r, t exclu. or w and register r ? w ? t z 110110 iiiiiiii xorwi i exclu. or w and immediate i ? w ? w z 011111 trrrrrrr comr r, t complement register /r ? t z 010110 trrrrrrr rrr r, t rotate right register r(n) ? r(n - 1), c ? r(7), r(0) ? c c 010101 trrrrrrr rlr r, t rotate left register r(n) ? r(n+1), c ? r(0), r(7) ? c c 010000 1xxxxxxx clrw clear working register 0 ? w z 010001 0rrrrrrr clrr r clear register 0 ? r z 0000bb brrrrrrr bcr r, b bit clear 0 ? r (b) none 0010bb brrrrrrr bsr r, b bit set 1 ? r(b) none 0001bb brrrrrrr btsc r, b bit test, skip if clear skip if r(b)=0 none 0011bb brrrrrrr btss r, b bit test, skip if set skip if r(b)=1 none 100nnn nnnnnnnn lcall n long call subroutine n ? pc, pc+1 ? stack none 101nnn nnnnnnnn ljump n long jump to address n ? pc none 110000 nnnnnnnn call n call subroutine n ? pc, pc+1 ? stack none 110001 iiiiiiii rtiw i return, place immediate to w stack ? pc,i ? w none 11001n nnnnnnnn jump n jump to address n ? pc none note : w : working register b : bit position wt : watchdog timer t : target tmode : tmode mode register 0 : working register cpio : control i/o port register 1 : general register tf : timer overflow flag r : general register address pf : power loss flag c : carry flag pc : program counter hc : half carry osc : oscillator z : zero flag inclu. : inclusive ? ?? ? / : complement exclu. : exclusive ? ? ? x : don?t ca re and : logic and ? ?? ? i : immediate data ( 8 bits ) n : immediate address
MDT10P21 this spec ification are subject to be changed without notice. any latest information please preview http;//www.mdtic.com.tw p. 10 2004/1 ver. 1.3 10. electrical characteristics (operating temperature at 25 j ). sym description condition min typ max unit vdd operating voltage 2.3 6.3 v v il input low voltage pa, pb rt cc, /mclr vdd=5v vdd=5v - 0.6 - 0.6 1.0 1.0 v v v ih input high voltage pa, pb rtcc, /mclr vdd=5v vdd=5v 2.0 3.2 vdd vdd v v i il input leakage current vdd=5v +/ - 1 a v ol output low voltage pa, pb vdd=5v, i ol =20ma vdd=5v, i ol =5ma 0.4 0.1 v v v oh output high voltage pa, pb vdd=5v, i oh = - 20ma vdd=5v, i oh = - 5ma 3.8 4.5 v v i slp sleep current (wdt disable) v dd ? 2.3 ~ 6.3 v 0.1 1.0 m a i slp sleep current (wdt enable) v dd ? 2.3 v v dd ? 3.0 v v dd ? 4.0 v v dd ? 5.0 v v dd ? 6.3 v 1 3 8 17 36 m a m a m a m a m a v pr power edge - detector reset voltage 1.1 1.3 v twdt the basic wdt time - out cycle time v dd ? 2.3 v v dd ? 3.0 v v dd ? 4 .0 v v dd ? 5.0 v v dd ? 6.3 v 27.0 23.2 20.4 18.4 16.8 ms ms ms ms ms t flt /mclr filter v dd ? 5.0 v 600 ns icc comparator supply current (one comparator) vdd=5.0v 15 m a vref input reference voltage vdd=2.5v ~6.3v vdd - 0.8v v --- comparator response time v - =vdd/4, v+=v - 0.2v v - =vdd/2, v+=v - 0.2v v - =vdd3/4, v+=v - 0.2v v - =vdd - 0.8,v+=v 0.2v vdd=5.0v , v - = vref v+ = (pa0~pa3) 8 8 8 8 m s m s m s m s
MDT10P21 this spec ification are subject to be changed without notice. any latest information please preview http;//www.mdtic.com.tw p. 11 2004/1 ver. 1.3 11. operating current temperature ? 25 j , the typical value as followings : 11.1 osc ty pe ? rc ; wdt ?e enable; comparator ?e disable @ v dd ? 5.0 v cext. (f) rext. (ohm) frequency (hz) current (a) 4.7 k 10.5m 1.35 ma 10.0 k 5.36m 750 m a 3p 47.0 k 1.24m 250 m a 100.0 k 589k 180 m a 300.0 k 200k 130 m a 470.0 k 126k 120 m a 4.7 k 5.6m 7 70 m a 10.0 k 2.85m 460 m a 20p 47.0 k 640k 190 m a 100.0 k 300k 150 m a 300.0 k 104k 125 m a 470.0 k 64k 115 m a 4.7 k 1.68m 310 m a 10.0 k 834k 210 m a 100p 47.0 k 182k 125 m a 100.0 k 87.6k 118 m a 300.0 k 29.6k 110 m a 470.0 k 18.6k 105 m a 4.7 k 748k 200 m a 10.0 k 367k 155 m a 300p 47.0 k 80k 115 m a 100.0 k 38k 110 m a 300.0 k 12.8k 105 m a 470.0 k 8k 100 m a
MDT10P21 this spec ification are subject to be changed without notice. any latest information please preview http;//www.mdtic.com.tw p. 12 2004/1 ver. 1.3 11.2 osc type ? lf (c=20 p); wdt ?e disable ; comparator ?e disable voltage/frequency 32 k 455 k 1 m sleep 2.1 v 3.0ua @2.6v 32.0ua @2.2v 42.0ua ?? 1.0 m a 3.0 v 6.0ua 45ua 60ua ?? 1.0 m a 4.0 v 12.0ua 65ua 100ua ?? 1.0 m a 5.0 v 30.0ua 100ua 150ua ?? 1.0 m a 6.3 v 110ua 185ua 2 60ua ?? 1.0 m a 11.3 osc type ? xt (c=10 p); wdt ?e enable ; comparator ?e disable voltage/frequency 1 m 4 m 10 m sleep 2.1 v 65ua 200ua 360ua ?? 1.0 m a 3.0 v 136ua 350ua 650ua 3 m a 4.0 v 252ua 550ua 1.0ma 8 m a 5.0 v 422ua 820ua 1.6ma 17 m a 6.3 v 810ua 1.36 ma 2.2ma 36 m a 11.4 osc type ? hf (c=10 p); wdt ?e enable ; comparator ?e disable voltage/frequency 4 m 10 m 20 m sleep 2.1 v 200ua 450ua @2.2v 940ua ?? 1.0 m a 3.0 v 410ua 810ua 1.37ma 3 m a 4.0 v 620ua 1.30ma 2.0ma 8 m a 5.0 v 1ma 1.70ma 3.0ma 17 m a 6.3 v 1 .56ma 2.50ma 4.0ma 36 m a 11.5 power edge - detector reset voltage (not in sleep mode), @ v dd ? 5.0 v v pr ?? 2 .1~ 2.2 v v pr ?r v dd (power supply)
MDT10P21 this spec ification are subject to be changed without notice. any latest information please preview http;//www.mdtic.com.tw p. 13 2004/1 ver. 1.3 12. port a equivalent circuit pa0 - pa3 i/o control write data bus read data o/p latch d g d i/o control latch c k q q b qb g qb d input resistor port i/o pin data i/p latch vref compartor control + - s 0 1 comparator level ttl input level pa4 i/o control write data bus read data o/p latch d g d i/o control latch ck q qb q b g q b d input resistor port i/o pin data i/p latch ttl input level vref 3 2 1 0 s0 s1 cmr_4 cmr_5 3/4 vdd 1/2 vdd 1/4 vdd comparator enable
MDT10P21 this spec ification are subject to be changed without notice. any latest information please preview http;//www.mdtic.com.tw p. 14 2004/1 ver. 1.3 pa5 - pa7 i/o control write data bus read data o/p latch d g d i/o control latch ck q qb q b g q b d input resistor port i/o pin data i/p latch ttl input level port b equivalent circuit i/o control write data bus read data o/p latch d g d i/o control latch ck q qb q b g q b d input resistor port i/o pin data i/p latch ttl input level
MDT10P21 this spec ification are subject to be changed without notice. any latest information please preview http;//www.mdtic.com.tw p. 15 2004/1 ver. 1.3 13. mclrb and rtcc input equivalent circuit r ? 1 k schmitt trigger mclrb r ? 1 k schmitt trigger rtcc
MDT10P21 this spec ification are subject to be changed without notice. any latest information please preview http;//www.mdtic.com.tw p. 16 2004/1 ver. 1.3 14. external capacitor selection for crystal oscillator @ v dd ? 5.0 v osc. type resonator freq. capacity range 20 mhz 10 pf ~ 50 pf hf 10 mhz 20 pf ~ 50 pf 4 mhz 10 pf ~ 30 pf 10 mhz 10 pf ~ 50 pf xt 4 mhz 10 pf ~ 50 pf 1 mhz 20 pf ~50 pf 1 mhz 20 pf ~ 30 pf lf 455 k 20 pf ~30 pf 32 k 20 pf ~30 pf MDT10P21 osc1 osc2 c1 c2 to increase the stability of oscillator and the ability of anti - noise, the above values of the external capacitor are for reference only, but the higher capacitance also increases the start - up time.

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